HDL design, simulation, synthesis and on-hardware verification — Verilog and VHDL, from spec to timing-closed device.
Block-level and top-level design in Verilog and VHDL. Lint-clean, style-consistent, documented.
Testbench development, directed and constrained-random testing, waveform review and coverage closure.
Vivado, Quartus, Libero. Resource optimisation, floorplan and place-and-route.
Constraint authoring, static timing analysis, critical-path analysis and sign-off.
JTAG bring-up, ILA / logic-analyser integration and functional validation on the target device.
RTL hardening, lint clean-up and documentation for handoff to an ASIC flow.
| Vendor | Families |
|---|---|
| Xilinx / AMD | Artix-7, Kintex-7, Zynq-7000, Zynq UltraScale+, Kintex UltraScale |
| Intel / Altera | Cyclone IV/V/10, Arria 10, Stratix 10 |
| Microchip / Microsemi | PolarFire, PolarFire SoC, IGLOO2 |
| Lattice | ECP5, CrossLink-NX, iCE40 |
Block diagram, interface definitions and timing requirements agreed before HDL starts.
Verilog / VHDL, lint-clean, style-consistent and reviewed.
Functional verification with directed and random testbenches. Waveform review at each milestone.
Resource utilisation, constraint-driven optimisation, timing check before place-and-route.
Static timing analysis, fix iterations until all paths meet constraints.
Device programming, JTAG debug, ILA probing and integration with the carrier board.
We will scope the RTL deliverables and timeline.
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